A semiconductor device having a backside electrode disposed on a silicon substrate is well known. Specifically, in the device, current flows in a thickness direction perpendicular to the substrate. The device is manufactured such than, in a step of polishing a backside of the substrate, firstly, the backside of the substrate is roughly polished. Then, the backside of the substrate is finely polished with a fine grinding stone having the number #2000, which is defined in Japanese Industrial Standard. Thus, two-step polishing is performed. Thus, the silicon substrate is polished so that the thickness of the silicon substrate becomes a predetermined thickness. After that, the backside electrode is formed on the backside of the substrate.
In the above method, when the backside of the substrate is finely polished, a small dislocation and/or a small defect may be formed on the backside of the substrate so that amorphous silicon layer is formed on whole of the backside of the substrate. In this case, the backside electrode is formed on the amorphous silicon layer, so that an interface between the amorphous silicon layer and the backside electrode has a large potential barrier height. This barrier height provides a Schottky barrier. Thus, an on-state resistance of the semiconductor device becomes large.
To avoid the above problem, two methods are disclosed in, for example, U.S. Pat. No. 6,927,167 and Japanese Patent No. 3339552. In U.S. Pat. No. 6,927,167, after a step of polishing two times, a substrate is etched with etchant so that the amorphous silicon layer is removed. After this wet-etching step, a backside electrode is formed on the substrate. However, in this case, a wet-etching step is added to a manufacturing process of the device. Further, the thickness of the silicon substrate becomes thin. Furthermore, the thickness of the substrate is controlled by an etching time in the wet-etching step, so that the thickness of the substrate may be varied. Thus, it is difficult to control the thickness of the substrate accurately. Furthermore, it is not preferable for the silicon substrate to become thin when the thickness of the substrate is restricted to a predetermined thickness in view of warpage and/or durability.
In Japanese Patent No. 3339552, after a backside electrode is formed on a substrate, the substrate with the backside electrode is annealed at a temperature in a range between 400° C. and 500° C. so that metal in the backside electrode is alloyed with silicon in the substrate. An annealing step is added into the manufacturing process of the device. Further, an aluminum conductor of the device may be damaged by high temperature annealing, and a surface protection film on the device may be damaged by the high temperature annealing. Specifically, aluminum in the aluminum conductor may be diffused into the silicon substrate.